Semiconductor integrated circuit device

ABSTRACT

A semiconductor memory device is provided including a memory having memory cells and circuit blocks, a power switching circuit and a refresh control apparatus. In a first operation state, the refresh control apparatus supplies power to the memory using the power switching circuit to refresh the memory cells. In a second operation state, the refresh control apparatus turns off the power supply to at least one circuit block using the power switching circuit. Another operation state is also provided in which round transition between the first and second operation states is repeated multiple times. Accordingly, power consumption is reduced, especially for semiconductor memory devices that use memory elements in which a lengthy period is required for the refresh operation. As a result, it is possible to decrease the overall electric power of the semiconductor device.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device. Inparticular, the present invention relates to a semiconductor memorydevice having also a low electric power characteristic.

BACKGROUND ART

In general, as regards a dynamic memory, which stores information bycharge accumulated in a capacitor, it is necessary to perform refreshoperation in order to hold information in the memory. During the refreshoperation, power is supplied to the memory, and data in the memory isread and rewritten at intervals of about 64 ms. FIG. 3 shows a timerelation of power-on. A horizontal axis indicates time; tREF representsa period during which refresh operation is being performed; tNOMrepresents a period during which the refresh operation is not performed;and represents a period during which power supply is being turned on.Such an example is shown in, for example, “Hitachi IC Memory Data Book2”, Hitachi, Ltd., pp. 239, September 1997.

On the other hand, as regards an EEPROM and a flash memory, which storesinformation by electrons accumulated in a floating gate in general,information in the memory is held for about 10 years even if power isnot supplied to the memory. Such an example is shown in, for example,“Hitachi IC Memory Data Book 3”, Hitachi, Ltd., pp. 147, September 1996.

DISCLOSURE OF INVENTION

At present, a memory cell, which uses a data storage concept of adynamic memory (DRAM: Dynamic Random Access Memory), is widely studied.There is a high possibility that a memory cell, which is capable ofstoring information even if a period for refresh operation is muchlonger (for example, 10 seconds) than the present refresh interval ofabout 64 ms, is developed.

In this case, in particular, the DRAM has a disadvantage of powerconsumption during a standby state.

FIGS. 3 through 5 are diagrams illustrating relations between refreshand power supply control when various memory elements are used. FIG. 3illustrates a relation found in the conventional DRAM; FIG. 4illustrates a relation found when a memory element, of which a periodfor refresh operation is longer than the present refresh interval ofabout 64 ms, is used; and FIG. 5 illustrates a relation according to thepresent invention. By the way, in these diagrams, tREF represents aperiod for refreshing memory; tNOM represents a standby period; andPWRON represents a period during which power supply is being turned on.

To be more specific, for example, if a dynamic memory of which a periodfor refresh operation is 10 seconds could be realized, and if theconventional technique is used, the following operation is required tohold information accumulated in the dynamic memory: supplying power tothe dynamic memory; and performing refresh operation once every 10seconds. FIG. 4 shows a time relation of power-on of this example. Ahorizontal axis is time, and representations in FIG. 4 are the same asthose shown in FIG. 3. The refresh operation requires a large amount ofelectric power (hereinafter referred to as refresh electric power).However, due to sub-threshold leakage current, electric current flowinginto a constant current supply circuit, and the like, only supplyingpower to a circuit causes the circuit to consume a small amount ofelectric power (hereinafter referred to as standby power consumption).

As regards the DRAM of which characteristics are illustrated in FIG. 3,a ratio of the period tREF to the period tNOM is 1/6400. Because of it,the standby power consumption described above is little remarkable.However, on the other hand, in the method shown in FIG. 4, a ratio ofthe period tREF to the period tNOM is 1/1000000. Therefore, even ifstandby power consumption is 1/1000000 of refresh electric power, almostthe same amount of electric power as the refresh electric power will beconsumed in total as the standby power consumption.

In addition, also in the case of the flash memory, promotingminiaturization in a manufacture process, etc. causes film thickness ofan oxide layer enclosing the floating gate to become thin, resulting inshort data retention time. For example, if the data retention timebecomes one year, and if the conventional technique is used, the flashmemory will be used on the assumption that the data retention time ofthe flash memory is one year. This will cause degradation of a lifetimeof the product.

Main means used to solve the above-mentioned problems will be describedbelow.

The present invention relates to a semiconductor memory devicecomprising: a memory including a plurality of memory cells and aplurality of circuit blocks; a power switching means; and a refreshcontrol apparatus; wherein: said semiconductor memory device has a firstoperation state and a second operation state; in the first operationstate, the refresh control apparatus supplies power to the memory usingthe power switching means to refresh the memory cells; in the secondoperation state, the refresh control apparatus turns off the powersupply to at least one circuit block of the memory using the powerswitching means; and an operation state, in which round transitionbetween the first operation state and the second operation state isrepeated multiple times, is provided.

What is important in the present invention is that in the secondoperation state, the power supply to at least one circuit block of thememory is turned off.

Moreover, although the round transition between the first operationstate and the second operation state is repeated multiple times, thenumber of times is realistically considered as five times or more.

Furthermore, it is needless to say that, what is called, the DRAM, theflash memory, or other storage elements can be used as the memory cellaccording to present invention. A main point of the inventive concept ofthe present invention is a large reduction of the standby powerconsumption of the memory element. Therefore, as described above, if amemory cell having a characteristic that the period for refreshoperation of the memory cell is much longer than that of the refreshinterval (for example, for one second or more) is used, the presentinvention is extremely useful. If a memory cell, of which a period forrefresh operation is longer than the above (for example, 10 seconds ormore), is used, greater effect will be produced.

More specifically, the present invention is useful when using a memorycell having a characteristic that an interval between the first storageholding operation and the second storage holding operation of the memorycell is one second or more. Furthermore, the present invention is usefulwhen using a memory cell having a characteristic that an intervalbetween the first storage holding operation and the second storageholding operation of the memory cell is 10 seconds or more.

It is to be noted that the present invention is basically applied to aperiod over which only data holding is performed. In other words, as amatter of course, during operation such as read or write of the memory,etc., the power supply is not turned off. This can be understood judgingfrom the point of the present invention, that is to say, the reductionof standby power consumption.

For the purpose of reducing the standby power consumption, there are aplurality of methods for turning off power supply of a desire element.Embodiments of these various methods will be described as below.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram illustrating an embodiment that shows a basicconfiguration of the present invention.

FIG. 2 is a diagram illustrating another embodiment according to thepresent invention.

FIG. 3 is a diagram illustrating a relation between refresh and powersupply control performed in a conventional device.

FIG. 4 is a diagram illustrating a relation between refresh and powersupply control, which is expected when a period for refresh operation ofthe conventional device is long.

FIG. 5 is a diagram illustrating intermittent power control type refreshaccording to the present invention.

FIG. 6 is a configuration diagram illustrating another embodimentaccording to the present invention.

FIG. 7 is an example of a time chart in an embodiment shown in FIG. 6.

FIG. 8 is a sectional view illustrating an example of a memory cell thatconstitutes a memory array shown in FIG. 1.

FIG. 9 is a circuit diagram illustrating an example of the memory cellshown in FIG. 8.

BEST MODES FOR CARRYING OUT THE INVENTION

Before specifically explaining various modes of the present invention,main modes of the present invention will be listed as below.

Firstly, a first mode relates to a semiconductor memory device accordingto the present invention, characterized in that said memory comprises apower supply circuit that generates power supply required when readingfrom or writing to the memory cell; and a circuit block, of which powersupply is turned off in a circuit in the memory by a power switchingmeans in the second operation state, is the power supply circuit.

Secondly, a second mode relates to a semiconductor memory deviceaccording to the present invention, characterized in that said refreshcontrol apparatus comprises a timer; and in the second operation state,a part of power supply of the refresh control apparatus's circuit exceptthe timer is also turned off.

Thirdly, a third mode relates to a semiconductor memory device accordingto the present invention, characterized in that said memory cell is adynamic memory cell that stores information by charge accumulated in acapacitor; and a period for refresh operation of the memory cell is onesecond or more.

Fourthly, a fourth mode relates to a semiconductor memory deviceaccording to the third mode, characterized in that said memory cellcomprises a path for a first charge carrier; a node for storing chargethat generates an electric field where conductivity of the path ischanged; and a barrier structure through which a second charge carrierpasses in response to given voltage so that the second electron carrieris stored in the node; and said barrier structure presents an energyband profile comprising a first barrier component having a first barrierheight and a first width; and a second barrier component having a secondbarrier height higher than the first barrier height, and a second widthnarrower than the first width.

In this mode, a memory element used for this mode has advantages ofso-called DRAM level high speed, and flash memory level non-volatilityof the memory. In addition to it, it is possible to realize asemiconductor memory device, of which power consumption is low,according to the present invention.

Fifthly, a fifth mode relates to a semiconductor memory device accordingto the third mode, characterized in that said memory cell is a flashmemory cell that stores information in an electron stored in a floatinggate.

In this mode, it is possible to provide a semiconductor storage devicecharacterized by low power consumption and long life.

Sixthly, a sixth mode relates to a semiconductor memory device accordingto the first mode, characterized in that said memory cell is a memorycell having the following characteristics: a period for refreshoperation of the memory cell is longer than that of an interval forrefresh operation; and the period for refresh operation of the memorycell is one second or more.

Next, various modes of the present invention will be specificallyexemplified.

FIG. 1 is a configuration diagram illustrating an example of asemiconductor memory device according to the present invention. Thisexample comprises the following components. To be more specific, REFCrepresents a refresh control circuit (1); TIM represents a timer (2)used for its measurement of a period for refresh operation; PWRSWrepresents a power switching means (3); MEM represents a memory circuit(4) having a period for refresh operation that is sufficiently longerthan a period for refresh operation of the currently used DRAM; and PWRrepresents a power line (5). In this case, a period of refresh operationis 10 seconds as an example. As a specific configuration, the memorycircuit (4) comprises the following: a memory cell array MARY (7), whichis made up of many memory cells; a decoder DEC (8) that selects a partof the memory cells; a sense amplifier SA (9) that amplifies informationon the memory cell; an interface BUF (11) between the memory circuit MEM(10) and outside; and a power supply circuit GEN (12). It is to be notedthat use of general materials is sufficient to realize the specificconfiguration of this memory circuit (4).

The refresh control circuit 1 refreshes the memory circuit 4 in responseto time measured by the timer 2. More specifically, when time requiredfor refresh comes, in the first place, power is supplied to the memorycircuit 4 using the power switching means 3. After that, the memorycircuit 4 is refreshed. Finally, each power supply in the memory circuit4 is turned off using the power switching means 3 again. However, thepower supply is connected in such a manner that power is supplied fromthe power switching means 3 to each of element areas such as the memorycell array (7), the decoder (8), the sense amplifier (9), the interface(11), and the power supply circuit GEN (12), which are included in thememory circuit 4. FIG. 1 shows the connection of the power supplyexcluding this point.

FIG. 5 shows a time relation of power-on. FIG. 5 shows the same timerelation as those in FIGS. 3 and 4. In this manner, in this example,turning off electric power of a circuit during a period of tNOM permitsa ratio of standby power consumption to all power consumption to bereduced to nearly zero.

FIG. 2 is a diagram illustrating a second embodiment according to thepresent invention. If a memory cell, which will be used, is such thatholding contents stored in the memory cell becomes difficult when powersupply to the whole memory circuit is completely turned off, it isnecessary to supply power to the decoder and the sense amplifier. Thesecond embodiment is an example that is capable of coping with thiscase.

A difference with the example shown in FIG. 1 is that the power supplycontrolled by the power switching means 3 is limited to the power supplycircuit 12 in the memory circuit 4.

A circuit, which consumes highest standby power consumption, is oftenthe power supply circuit 3 that includes so-called analog circuits suchas constant current supply circuit. Turning off power supply of thepower supply circuit 12 (GEN) permits standby power consumption to bereduced efficiently, whereby same effects as those produced by theexample shown in FIG. 1 can be obtained.

In the present invention, for the purpose of reducing the standby powerconsumption, it is not necessarily required to limit a circuit, of whichpower supply should be turned off, to the power supply circuit. Even ifpower supply to the other circuit portion is turned off, it is(possibleto reduce power consumption in this portion. However, if the basicconcept of the present invention is applied, limiting it to a circuit,which can reduce more standby power consumption by turning off powersupply, is more efficient. In this sense, as described above, turningoff the power supply of the power supply circuit 12 in the memorycircuit 4 is more effective.

Additionally, although power is constantly supplied to the refreshcontrol circuit 1 in FIG. 1, it does not relate to the main points ofthe present invention in particular. This means that it is possible touse the other configurations arbitrarily. For example, there is also thefollowing method: power is supplied only to the timer 2; and power ofthe refresh control circuit 1 is supplied according to an instruction bythe timer 2. In short, the power supply is controlled so that duringperiods other than the period for refresh operation, power is suppliedto only circuits such as the timer 2, of which power supply cannot beturned off, and so that power to the other circuits is turned offwherever practicable.

In the above description, memory operation such as read and write is notdescribed. However, a problem between these is operation of generalsemiconductor storage devices. In the above-mentioned definitions (thatis to say, tREF is a period over which refresh operation is performed,and tNOM is a period over which the refresh operation is not performed),periods for operation such as read and write are included in tNOM.However, it applies to a period over which basically only data holdoperation is performed. As described above, of course, in the presentinvention, power supply is not turned off during operation includingread and write. The period, over which basically only data holdoperation is performed, represents a period that is called, for example,a standby state, a sleep state, or a hibernation state.

In addition, in order to perform operation shown in FIG. 5, power-onsteps, which are based on the assumption that transition from tNOM totREF occurs, are not particularly limited. In the present invention,power-on control such that refresh operation is normally performed isonly required.

An example shown in FIG. 6 is an embodiment in which how to use theexample in FIG. 2 is described more specifically. During normaloperation that performs read and write of the memory circuit 4, power isalways supplied to the power line (PWR: 20). Reference numeral 21 is apower supply selector (PEX); 22 is a battery (BAT: 22); 23 is a voltagedetecting circuit (SENS); and 202 is a second power line.

When power is supplied to the power line 20, the power line 202 issupplied with power from the power line 20. In addition, when the powersupply from the power line is turned off, the power line 2 is suppliedwith power from the battery 22.

On the other hand, the voltage detecting circuit 23 performs thefollowing: monitoring potential of the power line 20; detecting that thepower supply of the power line 20 has been turned off; and theninstructing the refresh control circuit 1 to perform periodical refreshoperation. The refresh operation at this time is similar to that shownin FIG. 5.

FIG. 7 illustrates an example of a specific operation waveform of theembodiment shown in FIG. 6. This example is based on the assumption thata power-supply voltage of the power line is 3.3 V, and that a voltage ofthe battery 22 is 3 V. V (GEN) represents voltage of power supply thatis fed to the power supply circuit. V (MISC) represents voltage of powersupply that is fed to circuits in the memory circuit other than thepower supply circuit. V(TIM) represents voltage of power supply that isfed to the timer 2. Additionally, PWR and PWR2 represent voltage at eachpower line.

When the power supply of the power line 20 is turned off at a point A,the power supply to the power line 2 is switched by the power supplyselector (21) PEX. That is to say, the power supply selector (21) PEXswitches its power-supply destination. As a result, power is suppliedfrom the battery 22BAT to the power line 2. Accordingly, potential ofthe power line 2 changes from 3.3 V to 3 V. The voltage detectingcircuit 23 detects that the power supply of this power line has beenturned off. The refresh control circuit 1 is notified of its result. Inresponse to the result, the refresh control circuit 1 turns off thepower supply of the power supply circuit using the power switching means3 (SW), and then starts a refreshing cycle as shown in FIG. 5. In otherwords, when refresh operation starts like a point B shown in FIG. 7, thepower supply to the power supply circuit is restarted for the refreshoperation. After that, when the refresh operation is completed, thepower supply to the power supply circuit is turned off again (C pointshown in FIG. 7).

Such operation permits data existing in the memory circuit 4 to be heldeven if the power supply of the power line is turned off in the standbystate, the hibernation state, or the like. In addition, it is possibleto reduce electric power consumption in this state to a minimum levelthat is required for holding data by means of intermittent power controlusing the refresh control circuit 1, the power switching means 3, etc.

If the memory circuit and the method for controlling the memory circuitaccording to the present invention is used for a small personalcomputer, it is possible to reduce electric power consumption in thestandby state, and in the hibernation state. Therefore, a batterylifetime of the personal computer can be lengthened. Moreover, becausedata in the memory circuit is held even in the standby state, thehibernation state, etc., it is possible to shorten returning time fromany one of those states to the operation state.

If the period for refresh operation according to the present inventionas shown in FIG. 5 continues for a long time (for example, five hours),information on the memory circuit 4 is stored in the hard disk onstandby before the refresh operation shown in FIG. 5 is also stopped. Inthis case, the data existing in the memory circuit 4 is erased.Therefore, when returning to the operation state, it is necessary toload the data, which has been stored in the hard disk, into the memorycircuit 4. It takes a long time to return. However, it such a long time(for example, five hours) is not spent, the returning time does notoften cause a problem in particular. The control produces an advantagethat it is possible to reduce electric power consumption required forrefreshing.

Furthermore, if a back-up medium such as a hard disk is provided, it ispossible to store the data, which exists in the memory circuit 4, in thehard disk on standby when electric power for continuing refreshoperation, which is performed by the intermittent power controlaccording to the present invention, is stopped. For example, concerningthe refresh operation by the intermittent power control, a batterylifetime is checked at each refresh operation. In that case, if it isjudged that only electric power, which is equivalent to an electricpower level required for storing the data existing in the memory circuit4 in the hard disk on standby, remains in the battery, the refreshoperation by means of the intermittent power control is stopped, andthen the data existing in the memory circuit 4 is stored in the harddisk on standby. This control method enables us to completely preventthe data existing in the memory circuit 4 from being erased.

In the above-mentioned embodiment, the medium is not particularlylimited to the hard disk. If a medium can store data inside the medium,the medium can be applied even if the medium is not supplied with power.For example, a flash memory is applicable.

In addition, in the above-mentioned embodiment, the timer 2 is used tomeasure a period for refresh operation. However, the measurement is notparticularly limited to this method. The following method can also beused: instead of the timer 2, equipping with a circuit that can monitorcharacteristics of the memory cell in the memory circuit; detecting thatthe data saved in the memory cell will be erased; and determining theperiod for refresh operation described above. Using an adaptive refreshcircuit like this enables optimization of the period for refreshoperation. Because of it, refresh electric power by means of theintermittent power control can be further reduced.

Generally, there are two kinds of methods for refreshing a dynamicmemory. One method is distracted refreshing. In this method, one-timerefreshing refreshes only one row address, and all row addresses arerefreshed in a predetermined period for refresh operation. The othermethod is concentrated refreshing. In this method, all row addresses arerefreshed continuously in a certain period of time, and this isperformed during a predetermined period for refresh operation.

On the other hand, because electrical charge and discharge of capacityof the power supply are required for turning on/off power supply,comparatively large electric power is consumed. Therefore, decreasingthe number of times the power supply is turned on/off as many aspossible permits the electric power consumption to be reduced.

According to these facts, in the embodiment described above, by adoptingthe concentrated refreshing, the number of times the power supply isturned on/off can be reduced. Therefore, the refresh electric power bymeans of the intermittent power control according to the presentinvention can be reduced.

The memory circuit 4 described above is not limited to a dynamic memory.As described above, a memory having a relatively long period for refreshoperation is applicable. A configuration of the memory cell itself doesnot matter. As a configuration of the memory circuit 4, for example, theabove-mentioned flash memory having data retention time of only aboutone year is applicable. Even if the flash memory having short dataretention time like this is used, by using, for example, a basicconfiguration according to the present invention as shown in FIG. 6, aflash memory system having data retention time of 10 years can be built,with only small capacity internal power supply, that is, a battery (BAT)equipped. In this manner, according to the present invention, it ispossible to provide a semiconductor storage device, of which dataretention time is long, and of which power consumption is low.

FIGS. 8 and 9 shows an example of the memory circuit 4, which usesanother example as a memory cell. This is an example, in which thememory circuit 4 described above is configured using a semiconductordevice that is abbreviated as a so-called PLED (Planar LocalizedElectron Device) element. The circuit like this is designated as PLEDmemory.

This PLED element is a semiconductor device, of which stored informationbecomes low leakage; to be more specific, charge accumulated in astorage node becomes low leakage. This can be said to be a semiconductordevice characterized in that said semiconductor device has a layeredstructure comprising a insulated layer and a semiconductor layer; saidlayered structure is placed between an electrode structure and an chargestorage node; and by means of barrier height control for a carrierpossessed by the layered structure, electric current, which flowsbetween the electrode structure and the charge storage node, iscontrolled.

The layered structure is considered that it is possible to switch itsoperation mode between an operation mode having a high barrier heightfor the carrier and an operation mode having a lower barrier height ascompared with this, and that this switching function permits theelectric current, which flows between the electrode structure and theelectron storage node, to be controlled. By the way, this PLED itself isdisclosed in, for example, Japanese Patent Application Laid-Open No. Hei10-200001, or “PLED-Planer Localized Electron Devices”, IEDM Tech. Dig.,pp.179-182, 1997, etc.

In this mode, a memory element used for this mode has advantages ofso-called DRAM level high speed, and flash memory level non-volatilityof the memory. It is not necessary to keep the power supply constantlyturned on for memory holding. In addition, although refreshing thememory is required, it is made practical use in about once a day, oronce a week, for example. Therefore, for example, the following becomespossible: keeping only the power supply of the timer in thesemiconductor memory device turned on constantly; and turning on thepower supply of the memory during the period for refresh operation,which permits the power supply of the memory to be turned off during theother periods. Thus, it is possible to reduce the power consumption ofthe semiconductor device to an extremely low level as compared with thelevels achieved by the conventional semiconductor memory devices or thelevels by means of the conventional driving methods.

FIG. 8 shows a sectional view of an example of the memory cell likethis. FIG. 9 shows a circuit diagram of the memory cell. In FIG. 8,reference numeral 40 represents a semiconductor substrate; 30 representsa bit line; 31 represents an insulated barrier layer; 32 representsintrinsic poly-silicon; 33 represents a charge storage node; 34represents an oxide layer; 35 represents a word line; 35 and 36represent sense lines; and 37 represents a ground electrode. The senseline 36 and the grounding conductor 37 depend on an impurity implantedregion formed on the semiconductor substrate 40. These correspond to asource and a drain in a general insulated-gate field-effect-transistordevice. Therefore, a manufacturing method similar to that of the generalinsulated-gate field-effect-transistor device is sufficient. By the way,in FIG. 8, in order to make understanding of an outline of thissemiconductor storage device easy, the semiconductor substrate 50 and alaminated area, which is laminated on the semiconductor substrate 50,are illustrated so that their directions intersect. To be more specific,in an actual configuration, a direction of a line connecting the senseline 36 with the grounding conductor 37 intersects a direction to whichthe word line 35 extends.

In an insulated-gate field-effect-transistor (typified by MOStransistors) structure, in which a source, a drain, and a gatecorrespond to the ground electrode 37, the sense line 36, and the chargestorage node 33 respectively, a PLED element having a layered structureis formed on a top surface of the charge storage node 33 correspondingto the gate; and the PLED element comprises the charge storage node 33,the tunnel layer 30, the intrinsic poly-silicon, and the bit line.Moreover, the word line 35, which controls electric current flowing tothe terminals BIT at both ends of the PLED element and to the electronstorage node 33, is additionally formed so that the word line 35 coversthe PLED element.

If a memory element is configured using this PLED element, an example asdescribed below is proposed. To be more specific, it is a semiconductorstorage device, wherein said memory element comprises: a path for afirst charge carrier; a node for storing charge that generates anelectric field where conductivity of the path is changed; and a barrierstructure through which a second charge carrier moves in response togiven voltage so that the second charge carrier is stored in the node;and said barrier structure has an energy band profile comprising: afirst barrier component having a first barrier height and a first width;and a second barrier component having a second barrier height higherthan the first barrier height, and a second width narrower than thefirst width.

FIG. 9 shows a circuit diagram of the memory cell illustrated in FIG. 8.A portion 43, which is enclosed with a dotted line in FIG. 9, indicatesthe memory cell. On a memory cell array portion, many memory cells likethis are arrayed, for example, in a matrix form. In FIG. 8, referencenumeral 40 shows the PLED element schematically. The specific structureof this element is shown in FIG. 8. A reference numeral 41 is parasiticoverlap capacitance between the charge storage node 33 and the word line35 shown in FIG. 8, and saves charge as data in the capacity. As regardsthe writing to the memory, high potential is applied to the word line35. Potential in response to the data to be written to the bit line 30is applied to. This causes the PLED element 40 to enter an ON state. Asa result, charge is transferred from the bit line 30 to the chargestorage node 33.

During read operation, potential is applied to the word line 35, andthen an insulated-gate field-effect transistor 42 (the MOS transistor isa typical example), which is indicated by the reference numeral 42(MOS1), is turned on or off in response to the charge accumulated in thecapacitor (CAP) 41 to read the data through the sense line 36. By theway, the insulated-gate field-effect transistor 42 and the so-calledPLED element are connected to each other via the node 44.

Moreover, it is needless to say that the example, which uses the PLEDelement, can use various configurations illustrated in FIG. 1, 2 or 6described above.

In this manner, according to the present invention, it is possible toprovide a semiconductor memory device, of which power consumption islow.

Industrial Applicability

As described above, the present invention can provide a semiconductormemory device, of which power consumption is low. Furthermore, thepresent invention can provide a semiconductor storage device, of whichpower consumption is low.

What is claimed is:
 1. A semiconductor memory device comprising: amemory comprising a plurality of memory cells and a plurality of circuitblocks; a power switch; and a refresh control apparatus; wherein: saidsemiconductor memory device has a first operation state and a secondoperation state; in the first operation state, the refresh controlapparatus refreshes the memory cells; in the second operation state, therefresh control apparatus turns off power supply to at least one circuitblock of the memory using the power switch; said semiconductor memorydevice has an operation state, in which round transition between thefirst operation state and the second operation state is repeatedmultiple times; and each of said memory cells is a memory cell having acharacteristic that an interval between a first storage holdingoperation and a second storage holding operation of the memory cell isone second or more.
 2. A semiconductor memory device according to claim1, wherein: said memory comprises a power supply circuit that generatespower supply required when reading from or writing to the memory cells;and a circuit block, to which power supply is turned off in a circuit inthe memory by said power switch in the second operation state, is thepower supply circuit.
 3. A semiconductor memory device according toclaim 1, wherein: said refresh controller comprises a timer; and in thesecond operation state, a part of power supply of the refreshcontroller's circuit except the timer is also turned off.
 4. Asemiconductor memory device according to claim 1, wherein: each of saidmemory cells is a dynamic memory cell that stores information by chargestored in a capacitor; and a period for refresh operation of each of thememory cells is one second or more.
 5. A semiconductor memory deviceaccording to claim 4, wherein: each of said memory cells comprises: apath for a first charge carrier; a node for storing charge thatgenerates an electric field where conductivity of the path is changed;and a tunnel barrier structure through which a second charge carrierpasses in response to a given voltage so that the second charge carrieris stored in the node; and said tunnel barrier structure presents anenergy band profile comprising: a first barrier component having a firstbarrier height and a first width; and a second barrier component havinga second barrier height higher than the first barrier height, and asecond width narrower than the first width.
 6. A semiconductor memorydevice according to claim 4, wherein: each of said memory cells, whichare semiconductor storage elements, has a layered structure comprising ainsulated layer and a semiconductor layer; said layered structure isplaced between an electrode structure and a charge storage node; and thelayered structure has barrier byte control for a carrier, which controlselectric current flowing between the electrode structure and the chargestorage node.
 7. A semiconductor memory device according to claim 1,wherein: each of said memory cells is a flash memory cell that storesinformation in a charge stored in a floating gate.
 8. A semiconductormemory device according to claim 1, wherein: each of said memory cellsis a memory cell having a characteristic that an interval between thefirst storage holding operation and the second storage holding operationof the memory cell is ten seconds or more.